The present invention generally relates to fabrication methods and resulting structures for semiconductor devices. More particularly, the present invention generally relates to direct bonded heterogeneous integration chip packaging structures and processes that do not utilize an interposer containing through-vias.
Packaging is one of the final manufacturing processes transforming devices into functional products for the end user. Packaging must provide electrical and photonic connections for signal input and output, power input, and voltage control. It also provides for thermal dissipation and the physical protection required for reliability.
In the electronic packaging field, there is a drive to develop thinner and larger structures. In 3D chip stacks, chips or dice are layered on top of one another in a three-dimensional stack with electrical interconnects between layers. This configuration has many benefits, such as providing a designer with the ability to place an increased number of chips in a given two-dimensional area with an increased amount of electrical communications between them. In 2.5D packages, an interconnect substrate known as an interposer is used to provide the high density interconnects. The interposer is placed between another underlying substrate and the dies, where the interposer contains through silicon vias (TSVs) connecting the metallization layers on its upper and lower surfaces.